Integrated circuit technology has produced a variety of semiconductor architectures for realizing micro-miniaturization of signal processing circuit designs. One such architecture, termed the gate array, employs a semiconductor (e.g. silicon, gallium arsenide) wafer structure that contains dedicated areas on the chip within which are disposed elemental circuit devices (e.g. transistors, gates, flip-flops), interconnect highways and power bus links. By the selective intercoupling of these device links and highways a prescribed signal processing circuit design is mapped into an integrated circuit architecture. In a conventional gate array architecture, one portion of the available area of the chip contains a plurality of logic gates, such as a "sea" of gates or uninterrupted rows of gate cells, while another portion of the chip real estate is dedicated to wiring/interconnect channels through which the gates may be selectively interconnected to realize a multi-function logic circuit. In terms of gate cell layout, the chip will typically have a central portion thereof deducated to a logic function cell area, while input/output cells will be distributed around the perimeter of the central cell area.
Because of the variable complexity of signal processing circuit designs, gate array architectures have been sized to contain predetermined numbers of gate cells, each of which has a respective capacity sufficient to accommodate up to some maximum number of gate cells. Thus, to efficiently map a completed circuit design into an integrated circuit architecture, the circuit designer will select, from an inventory of preestablished gate array die sizes (e.g. 1K, 2.5K, 5K, 7.5K, 10K and 20K gate cell arrays), that architecture (die) size the number of gate cells of which is closest to but at least as large as the design number.
Unfortunately, maintaining such an inventory of fixed die sizes has a number of disadvantages. First of all, the inventory itself involves significant manufacturing overhead, since each die size is, in effect, a custom architecture requiring its own dedicated mask set. If a design error or processing error occurs, or in the event of a process enhancement, it will become necessary to rework the mask set for each die size. Moreover, because the input/output cells are distributed around the periphery of the chip, the number of such input/output cells that the die may contain is limited by the size of the die. Namely, circuit designs requiring large numbers of input/output devices may be realized through the use of large sized dies, a considerable portion of the logic function cell area of which may go unused.